Semiconductor chip for optoelectronics and method for production thereof

ABSTRACT

Semiconductor chip, particularly a radiation-emitting semiconductor chip, comprising an active thin-film layer ( 2 ) wherein a photon-emitting zone ( 3 ) is formed, and a carrier substrate ( 1 ) for the thin-film layer ( 2 ) that is arranged at a side of the thin-film layer ( 2 ) that faces away from the emission direction and that is connected thereto. At least one cavity ( 8 ) by means of which a plurality of mesas ( 4 ) is fashioned at the boundary between carrier substrate ( 1 ) and thin-film layer ( 2 ) is fashioned in the active thin-film layer ( 2 ) proceeding from the carrier substrate ( 1 ).

[0001] The invention is directed to a semiconductor chip for optoelectronics, particularly a radiation-emitting semiconductor chip, comprising

[0002] an active thin-film layer, particularly on the basis of In_(1−x−y)Al_(x)Ga_(y)P (whereby 0≦x≦1, 0≦y≦1 and x+y≦1 apply), wherein a photon-emitting zone is formed, and

[0003] a carrier substrate for the thin-film layer that is arranged at a side of the thin-film layer that faces away from the emission direction and that is connected thereto. It is also directed to a method for the simultaneously manufacture of a plurality of such semiconductor chips.

[0004] The carrier substrate is part of the semiconductor chip in and of itself and mechanical support for the thin-film layer, which itself no longer comprises a self-supporting layer at that side lying opposite the carrier substrate.

[0005] Thin-film layer on the basis of In_(1−x−y)Al_(x)Ga_(y)P (whereby 0≦x≦1, 0≦y≦1 and x+y≦1 apply) means that the thin-film layer comprises a plurality of layers that are manufactured of doped or undoped material from the system In_(1−x−y)Al_(x)Ga_(y)P (whereby 0≦x≦1, 0≦y≦1 and x+y≦1 apply).

[0006] Semiconductor chips of the species initially cited are disclosed by U.S. Pat. No. 5,008,718 and U.S. Pat. No. 5,367,580. For manufacturing a semiconductor chip of the known type, an active semiconductor layer sequence is usually applied on a substrate by means of an epitaxy process. Subsequently, a carrier substrate is secured on the upper side of the active semiconductor layer sequence. The substrate on which the semiconductor layer sequence had been deposited is at least partially removed.

[0007] A metallic reflection layer is advantageously situated between the carrier substrate and the active semiconductor layer sequence, so that no light is absorbed by the carrier substrate.

[0008] One disadvantage of the known semiconductor chip is that the metallic reflection layer arranged between carrier substrate and the active semiconductor layer sequence generally do [sic] not comprise a satisfactory reflectivity given short wavelengths. Particularly at a wavelength of less than 600 nm, gold becomes more and more inefficient as metallic reflection layer since the reflectivity significantly decreases. For example, the elements Al and Ag, whose reflectivity remains comparatively constant at wavelengths shorter than 600 nm, can be employed at wavelengths below 600 nm.

[0009] The bonding of large surfaces like the metallic reflection layer are presents difficulties. The bonding and the alloying of the metallic contact layer also results in a considerable risk for a deterioration of the quality of the metallic reflection layer.

[0010] DE 198 07 758 A1 also discloses a semiconductor shaped like a truncated pyramid that comprises an active, light-emitting zone between an upper window layer and a lower window layer. Together, the upper window layer and the lower window layer form a base body having the shape of a truncated pyramid. The result of the slanting alignment of the sidewalls of the window layers is that the light emanating from the active zone is totally reflected at the lateral surfaces and impinges the base surface of the truncated pyramid base body serving as luminous surface at nearly a right angle. As a result thereof, a part of the light emitted by the active zone emerges onto the surface within the exit cone of the semiconductor element.

[0011] What is thereby to be understood by exit cone here and below is the cone that is formed by light rays whose angle of incidence onto the exit face is less than the critical angle for the total reflection and that are therefore not totally reflected but directly coupled out from the semiconductor material. The aperture angle of the exit cone, consequently, is twice as large as the limit angle of the total reflection. Those light rays that proceed outside of the exit cone, i.e. impinge the exit face at an angle larger than the limit angle of the total reflection, are totally reflected.

[0012] In order to achieve a significant increase in the light yield, this concept assumes a minimum thickness for the upper and lower window layer. Given the known truncated pyramid semiconductor element, the thickness of the upper and lower window layer amounts to at least 50.8 μm (2 milli inches). Such a layer thickness is still doable. When, however, the power of the known semiconductor chip is to be increased, then it is necessary that all dimensions be scaled. Layer thickness thereby quickly derive that can only be manufactured with high outlay in an epitaxial way. If it can be scaled at all, then this known semiconductor chip can only be scaled with great technical outlay.

[0013] Proceeding from this Prior Art, the invention is based on the object of specifying a semiconductor chip manufacturable in thin-film technology that has an improved light output and in specifying a method for the manufacture thereof.

[0014] This object is inventively achieved with a semiconductor chip having the features of patent claim 1 and with a method having the features of patent claim 27.

[0015] Preferred embodiments and methods for manufacturing the semiconductor chip are the subject matter of the subclaims.

[0016] In an especially preferred embodiment of the semiconductor chip, the crossection of the cavity decreases from the outside to the inside, i.e. from the boundary to the carrier substrate toward the inside of the thin-film layer, and the depth of the cavity amounts to more than half the thickness of the thin-film layer.

[0017] The advantageous effect of the cavity or, respectively, the plurality of mesas produced by the cavity is that the thin-film layer comprises contact pressure layers at its connecting side toward the carrier substrate that are small in area compared to the overall crossectional area of the chip. This yields the advantage that a comparatively high local pressure can be generated in the region of the smaller contact pressure surfaces—this is required for a dependable joining of carrier substrate and thin-film layer—but that, simultaneously, the pressure on the thin-film layer can be keep sufficiently low in order to optimally preclude damage to the thin-film layer when it is joined to the carrier substrate.

[0018] On the other hand, the available connection surface is enlarged due to the cavity, which can likewise lead to an improvement in the connection between carrier substrate and thin-film layer. Moreover, the cavity is available for the acceptance of excess adhesive or solder material, which advantageously makes their dosing less critical.

[0019] The cavity also advantageously creates lateral surfaces at which a part of the radiation emitted by the active zone is deflected such that, within the exit cone, it impinge [sic] that exit face of the active thin-film layer that faces away from the carrier substrate. Compared to the Prior Art, the reflection at the lateral surfaces of the mesas given the semiconductor chip of the invention at least partly occurs at the location of the reflection at a continuous, planar reflection layer.

[0020] It is thereby advantageous when the lateral surfaces project as deeply as possible into the thin-film layer, so that an optimally great part of the radiation emitted by the active zone that is not directly incident onto the exit face and coupled out thereat is reflected such (potentially even multiply) that it impinges the exit face with an angle that lies within the exit cone.

[0021] Investigations show that the outfeed efficiency increases greatly when the depth of the cavity is greater than half the thickness of the thin-film layer.

[0022] Given an embodiment of the invention, the cavity is so deep that the active zone of the active thin-film layer is parted by it.

[0023] It has been shown that semiconductor chips whose active zone is interrupted by a cavity introduced into the active thin-film layer proceeding from the fastening side exhibit an especially high light yield. In this case, namely, it is not only the photons emitted toward the fastening side but also at least some of the photons emitted toward the exit face of the active thin-film layer that are redirected due to reflection at the lateral surfaces of mesas into an angle relative to the exit face that lies within the exit cone.

[0024] The reflection at the boundary surface of the mesas results therein that a large part of the photons emitted by the active zone is incident onto the exit face within the exit cone and can leave the semiconductor chip.

[0025] In another preferred embodiment, the thin-film layer is fashioned such that at least one trajectory of the photons emitted by the active zone leads from the respective mesa to one of the neighboring mesas.

[0026] As a result of the optical coupling of the mesas, photons that have not been reflected at one of the lateral surfaces of the original mesa can proceed into one of the neighboring mesas and are reflected such at the lateral surfaces of the respective mesa that they impinge the exit face within the exit cone.

[0027] In an advantageous development of the invention, further, the mesas are equipped with concave lateral surfaces.

[0028] As a result of these measures, rays that are initially reflected at the exit face become steeper and steeper relative to the exit face with every further reflection at a lateral surface of a mesa, so that they ultimately impinge the exit face within the exit cone.

[0029] In another preferred embodiment, the mesas are covered with a reflection layer.

[0030] As a result of this measure, all light rays incident onto the lateral surface of the mesas are steered in the direction onto the exit side of the semiconductor chip.

[0031] Further advantageous developments of the inventive semiconductor chip and of the inventive method derive from the exemplary embodiments described below in combination with the drawings. Shown are:

[0032]FIG. 1 a schematic illustration of a crossection through a semiconductor chip according to the invention;

[0033]FIG. 2 a schematic illustration of a crossection through a further exemplary embodiment of a semiconductor chip according to the invention, whereby the active zone is respectively arranged truncated pyramid-shaped mesas;

[0034]FIG. 3 a schematic illustration of a crossection through a semiconductor chip according to the invention that is equipped with mesas that comprise concave lateral surfaces;

[0035]FIG. 4 a diagram that shows the increase in the light yield given the semiconductor chips according to the invention compared to traditional semiconductor chips;

[0036]FIG. 5 a schematic illustration of a crossectional profile of a mesa that is composed of a lower, flat conoidal frustum and an upper, step conoidal frustum;

[0037]FIGS. 6a-6 d schematic illustrations of various crossectional profiles of mesas and a diagram that shows the dependency of the output efficiency on the radius of the boundary surface between the lower truncated pyramid and the upper truncated pyramid of the mesa from FIG. 5;

[0038]FIG. 7 a diagram that shows the dependency of the output efficiency on the reflectivity of a contact layer arranged on the peak of the mesa from FIG. 5;

[0039]FIG. 8 a diagram wherein the dependency of the output efficiency on the reflectivity of the lateral surfaces of the mesa from FIG. 5 is shown;

[0040]FIG. 9 a diagram from which the relationship between output efficiency and size of a luminous spot in the active zone proceeds;

[0041]FIGS. 10a-10 d schematic illustrations of various crossectional profiles of a mesa wherein the height of the active zone is varied, and a diagram wherein the output efficiency is shown dependent on the thickness of a lower limiting layer;

[0042]FIG. 11 a diagram that shows the dependency of the output efficiency on the sidewall angle of the lateral surfaces of a mesa having the crossectional profile shown in FIG. 10b;

[0043]FIG. 12 a further diagram wherein the dependency of the output efficiency on the sidewall angle of a mesa having the crossectional profile from FIG. 10b is shown;

[0044]FIG. 13 a diagram that illustrates the dependency of the output efficiency on the width of the active thin-film layer given constant height;

[0045]FIG. 14 a diagram that shows the dependency of the output efficiency on the thickness of a cover layer connecting the mesas for different profiles of the mesas;

[0046]FIG. 15 a schematic illustration of a crossection through a further exemplary embodiment of a semiconductor according to the invention;

[0047]FIG. 16 a schematic illustration of a crossection through a further exemplary embodiment of a semiconductor chip according to the invention;

[0048]FIGS. 17a-17 e a schematic illustration of sequence of a first method for the manufacture of a plurality of semiconductor chips according to the invention;

[0049]FIGS. 18a-18 e a schematic illustration of sequence of a second method for the manufacture of a plurality of semiconductor chips according to the invention;

[0050]FIGS. 19a-19 e a schematic illustration of sequence of a third method for the manufacture of a plurality of semiconductor chips according to the invention;

[0051]FIG. 20 an image of a semiconductor chip according to the invention from above;

[0052]FIG. 21 an image of an oblique view of a surface of a thin-film layer after the generation of cavities; and

[0053]FIG. 22 a magnified excerpt of the image of FIG. 21.

[0054] Identical component parts or component parts having the same effect are provided with the respectively same reference characters in the Figures.

[0055] The semiconductor chip shown in FIG. 1 for a light-emitting diode comprises a carrier substrate 1 on which the active thin-film layer 2 is applied. For the sake of clarity, the thickness of the active thin-film layer 2 is shown exaggerated in FIG. 1 compared to the thickness of the carrier substrate 1. The active thin-film layer 2 comprises a photon-emitting, active zone 3 that is respectively fashioned at a mid-height in mesas 4. The mesas 4 can be fashioned like a truncated pyramid or a conoidal frustum. The semiconductor chip thus represents a light-emitting diode.

[0056] The mesas 4 are arranged at a cover layer 5 that comprises a central, front-side contact location 7 on a flat front side 6 that is preferably formed by a metallization layer. The back-side mesas 4 formed by cavities 8 are covered with a reflection layer that is composed of a dielectric insulation layer 9 an a metallization layer 10 applied thereon. The insulation layer 9 is interrupted by through-contactings 12 formed by metallized sections along a base area 11 of the mesas 4.

[0057] The insulation layer preferably has a lower refractive index than the adjoining semiconductor layer of the thin-film layer 2. It is also fashioned as a diffusion barrier for the metallization layer 10. An electrically conductive layer can also be employed instead of the insulating layer 9. The optical properties of this layer are determinant.

[0058] For manufacturing the semiconductor chip shown in FIG. 1, the active thin-film layer 2 is first epitaxially grown on a growth substrate. The active thin-film layer 2 can, for example, be manufactured on the basis of InGaAlP. The cover layer 5 is thereby formed first on the growth substrate and is subsequently doped with a concentration above 10¹⁸ cm⁻³ in order to assure a good conductivity of the cover layer 5. A good conductivity of the cover layer 5, namely, is a prerequisite therefor that one central contact location 7 on the front side 6 of the light-emitting diode chip suffices for the supply of the active zone 3 of a plurality mesas 4 with current. Moreover, the composition of the cover layer 5 is selected such that it is transparent for the photons generated in the active zone. This can usually be accomplished via a setting of the band gap on the basis of the composition of the material of the cover layer 5.

[0059] Subsequently, a further layer is applied on the cover layer 5, the mesas 4 being formed in said further layer with suitable wet-chemical or dry-chemical etching processes. Such etching processes are known and are not the subject matter of the application. The mesas 4 are preferably fashioned only in the regions provided for the semiconductor chips and are in turn preferably formed therein only in the regions wherein the light outfeed can occur, i.e. not under contact layers 7, 43 and 49 on the upper side of the thin-film layer 2. The regions provided for the semiconductor chips typically have lateral dimensions of, for example, 400×400 μm². The mesas 4 comprise outside dimensions that lie in the region of the layer thickness of the active thin-film layer 2. The outside dimensions of the mesas 4 therefore lie in the region of 10 μm

[0060] The deposition of the insulating layer 9 on the mesas 4 and the formation of the through-contacting 12 ensues in a further method step. The metallization layer 10 is subsequently applied.

[0061] Subsequently, the active thin-film layer 2 is parted according to the intended plurality of semiconductor chips. This ensues, for example, by wet-etching.

[0062] The detached, active thin-film layers 2 are then secured to the carrier substrate 1, for example by eutectic bonding, and the growth substrate is removed by wet-etching. As a final step, the contact locations are formed on the exposed front side of the active thin-film layer 2, and the semiconductor chips are separated by parting the carrier substrate 1.

[0063] The semiconductor chip shown in FIG. 1 comprises the advantage that the photons generated by the active zone 3 do not impact components of the semiconductor chip that absorb said photons. The metallization layer 10, namely, keeps the photons away from the carrier substrate 1. Accordingly, the carrier substrate can be advantageously optimized very well in view of electrical and/or thermal conductivity and/or thermal expansion.

[0064] A further advantage is that, given the semiconductor chip from FIG. 1, a majority of the photons emitted by the active zone 3 is totally reflected at lateral surfaces 13 of the mesas 4. The photons totally reflected at the lateral surfaces 13 are incident onto the front side 6 at a large angle. In particular, a part of the photons that would be totally reflected at the front side without reflection at the lateral surfaces 13 impinges the front side 6 within the exit cone and can therefore leave the semiconductor chip. Given the semiconductor according to FIG. 1, the reflection at the continuous base surface known from the Prior Art is at least partially replaced by the total reflection at the lateral surfaces. Compared to traditional semiconductor chips without cavities 8, the semiconductor chip of FIG. 1 therefore exhibits a light yield that is increased by nearly the factor of 2.

[0065] Let the described effect be explained in detail below on the basis of the further exemplary embodiments shown in FIGS. 2 and 3.

[0066] Let a number of light rays be considered, whereby the term light rays should not be understood as a limitation to a specific wavelength but as a reference to the methods of geometrical optics, regardless of the wavelength.

[0067] Given the exemplary embodiment shown in FIG. 2, the mesas 4 are fashioned like a truncated pyramid and are secured to the carrier substrate 1 via a contact layer 4 only at the base area 11 of the mesas 4. The active zone 3 is supplied with current by the contact layer 14.

[0068] Due to the great differences between the refractive indices of semiconductors to casting resin of, typically, 3.5 to values of, typically, 1.5, only light rays that are incident onto the boundary surface within an exit cone having an aperture angle or approximately 16° can couple out from the semiconductor at the boundary surface between semiconductor and casting resin. Given an angularly equally distributed incidence of the light rays, this corresponds to approximately 2% of the light rays incident onto a surface unit.

[0069] Due to the mesas 4, the light rays emanating from the active zone 3 are steered in the direction onto the front side 6. What the mesas 4 effect is that the light rays incident onto the lateral surfaces 13 are redirected in the direction onto the front side 6 and impinge thereat within the exit cone, so that they can leave the semiconductor chip. The light yield can thereby be optimized by means of a suitable selection of the dimensions of the base area 11, of the angle of inclination of the lateral surface 13 and the height of the mesas 4 as well as the position of the active zone 3.

[0070]FIG. 2 shows a light ray 15 that is first totally reflected at the lateral surface 13 and is directed from there to the front side 6. At the front side 6, the light ray 15 impinges the boundary surface within the exit cone and can therefore leave the semiconductor chip. Without the total reflection at the lateral surface 13, the light beam 15 would have been totally reflected at the front side 6 and steered back to one of the reflection layers known from the Prior Art, where it would have been reflected again. In this respect, the reflection at the traditional, continuous reflection layer is replaced by the reflection at the lateral surfaces 13 given the exemplary embodiment shown in FIG. 2.

[0071] This is also true of a light ray 16 that is first reflected at the base surface 11 and then at the lateral surface 13. After the second reflection, the light ray 16 is also steered to the front side 6, where it is incident within the exit cone. Without the reflection at the lateral surface 13, the light ray 16 would likewise have been totally reflected at the front side 6 and steered back to a back-side reflection layer.

[0072] It is also advantageous that the mesas 4 are optically coupled via the cover layer 5. What is to be understood by optical coupling in this context is that at least one of the light rays emanating from the active thin-film layer 2 can proceed across as center line 17 from the region of one of the mesas 4 into the region of one of the neighboring mesas 4. Due to the optical coupling with the assistance of cover layer 5, namely, a light ray 18 that is not incident onto one of the lateral surfaces 13 of the respective mesas 4 can be incident onto one of the lateral surfaces 13 of one of the neighboring mesas 4 and be steered thereat to the front side 6, where it impinges within the exit cone. The light yield is therefore enhanced further due to the optical coupling via the cover layer 5.

[0073]FIG. 3, finally, shows a crossection through a modified exemplary embodiment of the semiconductor chip wherein the mesas 4 are fashioned like conoidal frustums with concave lateral surfaces 13. The fashioning of the lateral surfaces 13 leads thereto that a light ray 18 reflected back and forth between the front side 6 and the lateral surface 13 is increasingly redirected to the front side given approach to the center line 17 until it is incident onto the front side 6 within the exit cone. The same is true of light rays 19 that initially proceed via the cover layer 5 from respectively one mesa 4 to the neighboring mesa 4 and are brought thereat to the front side 6 in a large angle.

[0074]FIG. 4, finally, shows a diagram wherein a measured curve 20 shows the dependency of the light yield in relative units of the operating current given pulsed operation for a traditional light-emitting diode manufactured in thin-film technology. A further measured curve 21 illustrates the dependency of the light yield in relative units dependent on the operating current for a light-emitting diode according to the exemplary embodiment shown in FIG. 3. It can be learned from FIG. 4 that the light yield given the exemplary embodiments shown in FIG. 3 comprises [sic] approximately double the light yield of traditional semiconductor chips without cavities 8.

[0075] A number of investigations were carried out in order to find the best shape for the mesas 4. The results of these investigations are presented in detail below on the basis of FIGS. 5 through 14.

[0076] First, let the parameters that were varied in the investigations be explained on the basis of FIG. 5. FIG. 5 shows a crossectional profile of one of the mesas 4. In the illustrated case, the mesa 4 is composed of a lower conoidal frustum 22 and an upper conoidal frustum 23. The lower conoidal frustum 22 has a base area 24 adjoining the cover layer 5. The active zone 3 is formed in the upper conoidal frustum 23. A contact location 25 arranged on the base area 11 of the mesa 3 [sic] is also provided in FIG. 5.

[0077] The lateral surfaces 13 of the mesas 4 are composed of a sidewall 26 of the lower conoidal frustum 22 and sidewalls 27 of the upper conoidal frustum 23. The geometrical dimensions of the lower conoidal frustum 22 along a common boundary surface 28 are selected such that the sidewall 26 merges directly into the sidewall 27.

[0078] Various dimensions of the mesa 4 are referred to below. The radius of the base area 24 of the lower conoidal frustum 22 is referenced r_(n), the radius of the boundary surface 28 is referenced r_(t) and the radius of the base area 11 is referenced r_(p). Further, the mesa 4 can be subdivided into a lower limiting layer 29 between the base area 24 and the active zone 3 and an upper limiting layer 30 between the active zone 3 and the base area 11. The lower limiting layer 29 thereby comprises a height hu and the upper limiting layer 30 comprises a height h_(o). The overall height of the mesa 4, finally, is referenced H. It was consistently set equal to 6 μm in all investigations. A value of 2 μm was selected for the thickness h_(w) of the cover layer in all investigations wherein the thickness h_(w) was not varied.

[0079]FIGS. 6a through 6 d show the result of a calculation wherein the radius r_(p) of the base area was set equal to 5 μm and the radius r_(n) of the base area 24 was set equal to 20 μm. The radius r_(t) of the boundary surface 28 was varied between 6 and 18 μm corresponding to the crossectional profiles shown in FIGS. 6a through 6 c .

[0080] A refractive index of 3.2 was employed for the active zone 3 in the investigations. The refractive index of the lower limiting layer 29, of the upper limiting layer 30 as well as of the cover layer was equal to 3.3. Insofar as it was not varied, the reflectivity of the contact location 25 was employed with 0.3. The reflectivity of the base area 11 not covered by the contact location as well as of the sidewalls 26 and 27 was set to the value 0.8. What is thereby understood by reflectivity is the respective coefficient of reflection referred to the energy.

[0081] Further, the self-absorption of the active zone 3 was taken into consideration with an absorption coefficient of 10,000/cm. All investigations were implemented with photon recycling. An internal quantum efficiency of 0.8 was assumed therefor. The quantum efficiency in the generation of photons due to charge carrier recombination was not taken into consideration. The output efficiency η indicated in the diagrams is therefore equal to the ratio of the photons coupled out from the semiconductor chip to the number of photons actually generated. The values for the indicated output efficiency η would therefore still have to be multiplied by the factor 0.8 in order to arrive at the external efficiency.

[0082] It was also assumed that the reflection at the contact location 25 and the sidewalls 26 and 27 is angle-independent. The case that the dielectric insulating layer 9 is applied first on the mesas 4 and supplemented by the mirroring metallization layer 10 is therefore underestimated in the investigations in terms of its effect, since the total reflection occurring in this case was not taken into consideration in the investigations.

[0083]FIG. 6c shows a diagram in which the output efficiency η is entered over the radius r_(t) in a curve 31. The output efficiency of a normal thin-film semiconductor chip is also entered for comparison, the scatter therefor being determined only via the photon recycling. This thin-film semiconductor chip having the edge length 300 μm comprises the same epitaxial structure as the mesa 4 in the lower conoidal frustum 22 and upper conoidal frustum 23. It was assumed that the semiconductor chip is provided with a mirror at the p-side whose reflectivity amounts to 0.72. This value is the average of the reflectivity of a reflection layer and a contact layer weighted with the degree of occupancy, whereby the value 0.8 was employed for the reflectivity of the reflection layer and the value 0.85 was employed for the degree of occupancy of the reflection layer and the value 0.3 for the reflectivity of the contact layer and 0.15 for the degree of occupancy was employed.

[0084] It can be learned from FIG. 6 that, given a very large angle of incidence φ_(o) of the upper conoidal frustum 23 according to the crossectional profile shown in FIG. 6a, the output efficiency η is hardly better than the output efficiency η of a traditional thin-film light-emitting diode, whose output efficiency is shown with the straight line 32 in FIG. 6d. This is also easy to understand since the mesa 4 having the flat crossectional profile shown in FIG. 6a hardly converts the light rays emanating from the active zone 3 into a steep angle relative to the luminous surface 6. It is precisely this, however, that the mesa 4 with the crossectional profile shown in FIG. 6c accomplishes, for which reason the output efficiency η in this case amounts to nearly double the output efficiency 11 of a traditional thin-film light-emitting diode.

[0085] Further the dependency of the output efficiency η on the reflectivity of the contact location 25 was investigated. To this end, the output efficiency . was calculated dependent on the reflectivity of the contact location 25, whereby the crossectional profile of the mesa 4 was the same as the crossectional profile shown in FIG. 6b. It was also assumed that the contact location 25 covers the entire base area 11. It can be learned from FIG. 7 that the output efficiency η is not significantly dependent on the reflectivity of the contact location 25. The semiconductor chips described here having mesas 4 on the fastening side therefore seem to be significantly less sensitive to the poor reflectivity of the contact location than the traditional thin-film light-emitting diodes, since the multiple reflections leading to the outfeed occur only to a slight fraction between the base area 11 and the luminous surface 6 but three-dimensionally in the mesa 4.

[0086] The relative independence from the reflectivity of the contact location 25 is particularly advantageous since, in practice, a low ohmic resistance between the contact location 25 and the upper limiting layer 30 generally involves a poor reflectivity. A good ohmic contact, namely requires the diffusion of atoms from the layer forming the contact location 25 into the material lying therebelow.

[0087] In contrast to the dependence on the reflectivity of the contact location 25, the dependence of the output efficiency η on the reflectivity R_(S) of the mirror surfaces on the base area 11 and the sidewalls 26 and 27 is highly pronounced. This is shown by the results of a calculation that were [sic] carried out with a model for the semiconductor chip whose mesas 4 comprise the radii r_(p)=5 μm, r_(d)=16 μm and r_(n)=20 μm.

[0088] The mesas 4 therefore roughly exhibit the crossectional profile shown in FIG. 6b.

[0089] The result of this calculation is a curve 33 entered in FIG. 8, which monotonously rises with increasing reflectivity R_(S). A point 34 entered in the diagram from FIG. 8 represents the result of a calculation for a semiconductor chip on which no mirror layer was applied but that was embedded in resin as surrounding medium. However, total reflection occurs here, so that a higher output efficiency derives compared to a semiconductor chip with a mirror layer. This would also be the case given the exemplary embodiment shown in FIG. 1, whereby the electrical insulating layer, at which total reflection can likewise occur, is arranged between [sic] the metallization layer 10.

[0090]FIG. 9 contains the result of a calculation that what are referred to was carried out at a semiconductor chip having mesas 4 for whose radii the following applied: r_(p)=5 μm, r_(d)=16 μm and r_(n)=20 μm. The mesas 4 therefore essentially comprise the crossectional profile shown in FIG. 6. The active zone 3 was thereby located at mid-height between the base area 24 and the base area 11. In this calculation, the region wherein photons arise in the active zone was constricted to a luminous spot whose diameter d_(L) is entered on the abscissa. It can be seen on the basis of the diagram in FIG. 9 that the output efficiency is especially high given a small luminous spot. This means that photons in the center of the active zone 3 are coupled out especially well. In this respect, a slight Weierstrass effect is present.

[0091] Further, the influence of the position of the active zone 3 was investigated. FIGS. 10a through 10 c show various crossectional profiles wherein the thickness h_(u) of the lower limiting layer 29 and the thickness h_(u) [sic] of the upper limiting layer 30 were varied such that the overall height H of the mesa remained constant. The result of the calculation is shown in FIG. 10d, wherein the output efficiency η is entered dependent on the thickness h_(u) of the lower limiting layer 29. It turns out that the output efficiency η is only slightly dependent on the position of the active zone 3. An active zone 3 that lies in the lower half of the mesa 4 is to be preferred since the current density through active zone 3 is then low and the current load on the active zone can therefore be kept low, which avoids ageing and linearity problems.

[0092] Further, the influence of the angle of incidence φ_(o) of the sidewall 27 and of the angle of incidence φ_(u) of the sidewall 26 was investigated. A crossectional profile thereby formed the basis wherein the lower conoidal frustum 22 and the upper conoidal frustum 23 respectively comprise the same value for the angles of incidence φ_(u) and φ_(o). The radius φ_(o) of the active zone 3 was thereby kept constant at 10 μm and the angle of incidence φ=φ_(o)=φ_(u) was varied. Two cases were thereby considered. First the output efficiency η was investigated for the case of periodic boundary conditions, whereby the distance of the low end amounts to 10 μm. The result is presented in the curve 35 in the diagram in FIG. 11. An aperiodic case was also investigated. To that end, the output efficiency η of a semiconductor chip with a single mesa 4 was calculated, whereby all phontons [sic] entering into the cover layer 5 are absorbed by the cover layer 5. The aperiodic case is presented by the curve 36 in FIG. 11. It can already be seen from FIG. 11, that the cover layer 5 makes a noticeable contribution to the output efficiency η.

[0093] There is also an optimum range for the sidewall angle φ. This is clear on the basis of FIG. 12. In the underlying calculation, the radius r_(p) was set equal to 10 μm. The radius r_(a) of the active zone 3 and the radius r_(n) of the base area 24 were varied such that the angle of incidence φ of the sidewalls 27 and 26 covers a value range between 1.5° and 85°. As can be seen from FIG. 12, there is an optimum angular range for the angle of incidence φ. The sidewall angle φ should lie between 10° and 40°. Especially good values for the output efficiency η derive when the angle of incidence φ lies between 15° and 30°.

[0094] What influence a variation of the width of the mesas 4 has on the output efficiency η was subsequently investigated. In this case, therefore, the height H of the mesas 4 was kept constant and the radii r_(p), r_(a) and r_(n) were uniformly stretched. A curve 37 in FIG. 13 illustrates the case that the reflectivity R_(K) of the contact location is equal to 0.3. A further curve relates to that case wherein the reflectivity R_(K) of the contact location 25 amounts to 0.8. Both the curve 37 as well as the curve 38 show the dependency of the output efficiency η on the diameter 2r_(a) of the active zone 3. Given good reflectivity of the contact location 25, the output efficiency η drops only slightly with increasing diameter of the active zone 3. The curve 37, which illustrates the realistic case of a poor reflectivity R_(K) of the contact location, however, shows that the output efficiency η decreases greatly with increasing diameter of the active zone 3. The output efficiency η is therefore all the better the smaller the lateral expanse of the mesas 4 is.

[0095] The thickness of the cover layer 5 is also of significance for the output efficiency η . In FIG. 14, the output efficiency η is entered dependent on the thickness h_(w) of the cover layer 5 for various cases. A curve 39 reflects the aforementioned periodic case. A further curve 40 relates to the aperiodic case and a third curve 41 refers to a case wherein quadratic semiconductor chips having an edge length of 300 μm are connected to one another by a connecting layer. One can see from FIG. 14 that the cover layer 5 is increasingly advantageous with increasing layer thickness. In particular, it is advantageous when the layer thickness h_(w) is smaller than the height of the mesas 4, this amounting to 6 μm in the present case. It follows therefrom that the depth of the cavities 8 should be greater than half the thickness of the active thin-film layer 2.

[0096] However, it also proceeds from FIG. 14 that a plurality of individual semiconductor chips that respectively comprise a mesa 4 represent the best case, since the output efficiency is highest given the thickness h_(w)=0. Individual chips, however, has the disadvantage that their power cannot be arbitrarily increased since the dimensions of the semiconductor chips must also be scaled with the power. For practical reasons, however, the thickness of epitaxial layers is limited. This results therein that individual semiconductor chips cannot be designed for arbitrarily high powers. The semiconductor chips presented in FIGS. 1 through 4, however, can be nearly arbitrarily scaled, since the number of mesas 4 merely has to be increased corresponding to the increasing area of the cover layer 5 in order to raise the light power of the semiconductor chip.

[0097] A further investigation was directed to the question of whether the active zone 3 might not also be arranged in the cover layer 3. To that end, the output efficiency for a traditional thin-film light-emitting diode was calculated and this was set equal to 1. A semiconductor chip with the active zone 3 in the cover layer 5 has an output efficiency of 1.25 compared to the traditional thin-film light-emitting diodes. Finally, a relative output efficiency of 1.67 derived for the semiconductor chips shown in FIGS. 1 through 4. This shows that a boost of the output efficiency η can also be achieved when the active zone 3 is arranged in the cover layer 5.

[0098]FIG. 15 shows a preferred development of an inventive thin-film light-emitting diode in a schematic illustration. The thin-film layer 2 is thereby composed of an n-InGaAlP layer 2 a highly doped with Te (concentration >10¹⁷ cm⁻³, preferably >10¹⁸ cm⁻³) with a layer thickness of about 4 μm and an Mg-doped p-GaP layer 2 b with a layer thickness of about 3.5 μm.

[0099] As described in conjunction with FIG. 1, an insulating layer 9, for example of Si₃N₄, and a metallic reflector contact layer 10 are applied on the fastening side 11 of the thin-film layer 2 facing toward the carrier substrate 1. The Si₃N₄ layer, which comprises a thickness of preferably approximately three wavelengths of the emitted radiation with reference to the wavelength of the light emitted by the active zone, also leads—in addition to its electrically insulating effect—to an improved mirror effect of the metallic reflector and simultaneously represents a diffusion barrier between thin-film layer 2 and metallic reflector layer 10 given employment of a suitable material.

[0100] Alternatively, the insulating layer can be a layer stack of, for example, silicon nitride layers and silicon oxide layers in alternation.

[0101] The p-side current feed to the active zone 3 is assured by AuZn contacts 12 that are alloyed in and that are arranged at that surface of the mesas 4 facing toward the carrier substrate 1 and that are conducted through the insulating layer 9.

[0102] Preferably, the reflector contact layer 10 is an AuZn/TiW(N)/Au layer. However, it can also [ . . . ] completely of Au, Al or Ag or an alloy of these metals.

[0103] In order to achieve an adequate mechanical stability, the thin-film layer 2 is applied by bonding onto the conductive carrier substrate, an n-GaAs substrate in the exemplary embodiment. Upper side and underside of the carrier substrate 1 are thereby provided, for example, with AuGe contact layers 44, 45. Additionally, a TiPtAu/AuSn layer 47 is situated, for example, on the AuGe contact layer 45 at that side facing toward the thin-film layer 2.

[0104] A middle contact 7 and a metal frame 43 or some other electrically conductive frame that is connected to the middle contact 7 via two electrically conductive webs (not shown) is provided at the front or output side of the chip. The middle contact 7 and the metal frame 43 are composed, for example, of a TiPtAu layer and of a TiAuGe layer arranged between the former and the thin-film layer 2.

[0105] The high conductivity of the n-InGaAlP layers assures the required current divergence [sic]. The current feed to the p-side of the active zone 3 ensues via the contact layer 44 at the underside of the carrier substrate 1 and through the latter.

[0106] For further improvement of the light output, an optical anti-reflection coating 42 is arranged on the front side of the thin-film layer 2, a λ/4 layer of Si₃N₄ in the exemplary embodiment.

[0107] As already described in conjunction with FIG. 2, a plurality of cavities 8 shaped like a truncated pyramid are fashioned in the thin-film layer 2 proceeding from the connecting plane between carrier substrate and thin-film layer 2, said cavities 8 noticeably increasing the light output of the light-emitting diode. In the exemplary embodiment, the cavities 8 extend so far into the thin-film layer 2 that they interrupt the pn-junction 3. The cavities 8, however, can be fashioned only so deep that the do not part the pn-junction.

[0108] In addition to increasing the light output, the cavities 8 have the additional advantage that they substantially dismantle the stresses that occur in the eutectic bonding of the thin-film layer 2 onto the carrier substrate due to the different coefficients of thermal expansion of the various materials. The process dependability and the fabrication yield is [sic] thus enhanced.

[0109] The same is true of the compensation of mechanical stresses occurring during operation of the semiconductor chip due to different thermal expansions given temperature increase due to dissipated power.

[0110]FIG. 16 shows a further semiconductor chip of the invention in a schematic illustration. In this embodiment, the thin-film layer 2 is applied on an electrically insulating carrier substrate 1, so that the feed of current to the p-side of the pn-junction 3 ensues via a p-contact arranged on the Au—Ge contact layer 45 next to the thin-film layer 2.

[0111] The p-InGaAlP layer 2 b comprises a thickness of 6 μm; the n-InGaAIP:Te layer 2 a doped with 1×10¹⁸ cm⁻³ comprises a thickness of 3 μm. In this embodiment, the cavities 8 extend into a depth of 5.5 μm. They thus do not interrupt the pn-junction 3 in this embodiment.

[0112] In this embodiment, for example, an optical anti-reflection layer 48 of conductive indium-tin-oxide is applied on the front side of the thin-film layer 2 facing away from the carrier substrate 1, said layer 48 also contributing to the current divergence in addition to improving the light output. Consequently, the n-layer 2 a here can potentially be implemented thinner than given employment of an electrically insulating anti-reflection layer because the current divergence then need not ensue exclusively in the thin-film layer 2.

[0113] Such an electrically conductive anti-reflection layer 48 can also be utilized in all other embodiments of the inventive semiconductor chip. In the exemplary embodiment of FIG. 16, likewise, an insulating anti-reflection layer 42 can be utilized instead of the indium-tin-oxide layer 48.

[0114] The structure shown in FIG. 16 is also suitable given employment of a conductive carrier substrate 1 and is not limited to the employment of an electrically insulating carrier substrate 1.

[0115] The structure of the embodiment of FIG. 16 has the advantage that the carrier substrate 1 can be advantageously optimized particularly in view of thermal expansion and/or thermal conductivity without having to pay attention to its electrical conductivity.

[0116] As needed, the cavities 8 can be filled with a suitable material for the processing of the thin-film layer.

[0117] The method execution illustrated in FIGS. 17a through 17 e for the simultaneous manufacture of a plurality of inventive semiconductor chips shows schematic illustrations of perpendicular sections through a wafer at different points in time of the manufacturing method. For the sake of simplicity, a detailed illustration of, in particular, the active thin-film layer 2 as well as of the aforementioned layers between the carrier substrate and the thin-film layer in terms of all of their details has been foregone here as well as in the descriptions of the methods of FIGS. 18a through 19 e.

[0118] The thin-film layer 2, the insulating layer 9, the contact layers 7, 43-47 and 49 and the anti-reflection layer 42, 48, for example, are manufactured with traditional deposition methods known from semiconductor technology.

[0119] In a first sub-process, an active thin-film layer 2 is grown onto a growth substrate 20 (FIG. 17a). As explained farther above, such a thin-film layer 2 usually comprises a plurality of semiconductor layers having different compositions.

[0120] Subsequently, the cavities 8 are formed in the thin-film layer 2 for generating the mesas 4 in the regions wherein the light generation is to ensue later in the semiconductor chips. This ensues, for example, by means of a suitable mask technique and anisotropic wet-chemical etching (FIG. 17b).

[0121] At that side of the thin-film layer 2 provided with the cavities 8, the reflection layer 9, 10 (not shown here but see, for example, FIGS. 15 and 16) is then applied and the through-contactings 12 (not shown here but see, for example, FIGS. 15 and 16) are produced at the mesas 4 before this side is subsequently connected to a carrier substrate wafer 21 on whose principal faces contact layers 44, 45 are preferably situated (FIG. 17c).

[0122] After at least partial, preferably complete removal of the growth substrate 20, a bond pad 7 to which a power supply frame 43 is connected via terminal webs (see FIG. 20) is applied onto the uncovered surface of the thin-film layer 2 in every surface region in which a semiconductor chip is to be created, said frame 43 proceeding at the outer edge of the thin-film layer 2 of the later chip. Exemplary materials of such contact layers have already been cited above. The radiation output faces of the later chips that are situated between the bond pads 7 and the contacting frame 70 are provided with an optical anti-reflection coat 42. See FIG. 17d with respect thereto.

[0123] Before the separation of the wafer processed in this way, the thin-film layer 2 is parted, preferably by means of etching, along the parting paths 22, and a damage etching is implemented as warranted at the sidewalls of the thin-film layer that thereby arise. If necessary, the sidewalls of the thin-film layer 2 can be provided with an anti-reflection layer and/or a passivation layer.

[0124] After this step, the carrier substrate wafer 21 is then parted, for example by sawing or scoring and breaking along the parting paths 22, so that individual semiconductor chips 23 arise.

[0125] The complete manufacture of the semiconductor chips consequently advantageously ensues in the wafer union; i.e. the separation of the wafer into individual chips is the last step of the process before, for example, the chips are mounted in a housing at a later point in time.

[0126] The method shown in FIGS. 18a through 18 e differs from that of FIGS. 17a-17 e essentially in that the separate parting of the thin-film layer 2 before the parting of the carrier substrate wafer 21 is omitted, and the parting of the thin-film layer 2 together with the parting of the carrier substrate wafer 21 ensues in one step along the parting lines 22.

[0127] The method illustrated in FIGS. 19a through 19 e differs from that of FIGS. 17a-17 e essentially in that the separate parting of the thin-film layer 2 ensues before the joining of the thin-film layer 2 to the carrier substrate wafer 21.

[0128] Instead of ensuing by means of grinding and/or wet-chemical etching, the removal of the growth substrate can also ensue by means of pop-off. To this end, an absorbent layer that has a smaller band gap than the growth substrate is preferably introduced between the thin-film layer and the growth substrate. The absorbent layer is destroyed by means of a laser having a suitable wavelength that passes through the growth substrate. Given a growth substrate of GaAs, the absorbent layer is composed, for example, of InGaAs and the laser, for example, is an IR laser.

[0129] The mesas 4 generated by means of cavities 8 are visible in the view of an inventive chip from above that is shown in FIG. 20. What can be particularly seen is that no cavities 8 are present in the regions of the contact 7, of the connecting webs 49, of the power supply frame 43 and of the parting tracks. These are all regions in which little or no radiation would be coupled out anyway. The omission of the cavities in these regions advantageously leads to a clear mechanical stabilization of the thin-film layer 2. This has a positive effect particularly in the region of the contact 7 because a bond wire is usually put in place and pressed on there when the semiconductor chip is mounted in a housing.

[0130]FIG. 21 shows an image of an oblique view of a surface of a thin-film layer 2 after generating the cavities 8. Here, too, it can be seen that no mesas 4 are present in the regions of the terminal webs 49 and in the regions 90 of the power supply frame 43.

[0131]FIG. 22 shows an enlarged excerpt from FIG. 21. 

1. Semiconductor chip for optoelectronics, particularly a radiation-emitting semiconductor chip, comprising an active thin-film layer (2) wherein a photon-emitting zone (3) is formed, and a carrier substrate (1) for the thin-film layer (2) that is arranged at a side of the thin-film layer (2) that faces away from the emission direction and that is connected thereto, characterized in that at least one cavity (8) by means of which a plurality of mesas (4) is fashioned at the boundary between carrier substrate (1) and thin-film layer (2) is fashioned in the active thin-film layer (2) proceeding from the carrier substrate (1).
 2. Semiconductor chip according to claim 1, characterized in that the crossection of the cavity (8) becomes smaller over its course away from the carrier substrate (1).
 3. Semiconductor chip according to claim 1 or 2, characterized in that the active thin-film layer comprises a layer sequence of the basis of In_(1−x−y)Al_(x)Ga_(y)P (whereby 0≦x≦1, 0y≦1 and x+y≦1 apply).
 4. Semiconductor chip according to claim 1, characterized in that the cavities (8) are fashioned so deep that they part the active zone (3).
 5. Semiconductor chip according to one of the preceding claims, characterized in that mesas (4) are formed by means of a plurality of cavities (8) only in those regions that represent the radiation-generating regions of the thin-film layer (2).
 6. Semiconductor chip according to one of the preceding claims, characterized in that at least one trajectory (18) of the photons emitted by the active zone (3) leads from the respective mesa (4) to one of the neighboring mesas (4).
 7. Semiconductor chip according to claim 5 or 6, characterized in that the mesas (4) taper toward the carrier substrate.
 8. Semiconductor chip according to claim 7, characterized in that the mesas (4) comprise concave lateral surfaces (13).
 9. Semiconductor chip according to one of the claims 5 through 8, characterized in that the mesas (4) are fashioned in the shape of truncated pyramids.
 10. Semiconductor chip according to one of the claims 5 through 9, characterized in that the active zone is arranged in a half of the mesas (4) neighboring the cover layer (5).
 11. Semiconductor chip according to one of the claims 5 through 10, characterized in that the cover layer (5) is transparent to the farthest-reaching extent for the photons emitted by the active zone (3).
 12. Semiconductor chip according to one of the claims 5 through 11, characterized in that the cover layer (5) is highly doped.
 13. Semiconductor chip according to one of the claims 4 through 12, characterized in that the mesas (40 are covered with a reflection layer (9, 10).
 14. Semiconductor chip according to claim 13, characterized in that the reflection layer comprises a metallization layer (10) underlaid with an insulating layer (9).
 15. Semiconductor chip according to one of the preceding claims, characterized in that the active thin-film layer (2) comprises a thickness of between 5 μm and 50 μm.
 16. Semiconductor chip according to one of the preceding claims, characterized in that the active thin-film layer (2) comprises a thickness of between 5 μm and 25 μm.
 17. Semiconductor chip according to one of the preceding claims, characterized in that the depth of the at least one cavity (8) is greater than half the thickness of the thin-film layer (2).
 18. Semiconductor chip according to one of the preceding claims, characterized in that the carrier substrate (1) is electrically conductive and comprises an electrical contact surface (44) at that side facing away from the thin-film layer (2).
 19. Semiconductor chip according to one of the claims 1 through 17, characterized in that the carrier substrate (1) is electrically insulating or electrically conductive and comprises an electrical contact surface (46) next to the thin-film layer (2) at that side facing toward the thin-film layer (2).
 20. Semiconductor chip according to one of the preceding claims, characterized in that the surface of the thin-film layer (2) that lies opposite the fastening side (11) is provided with an optical anti-reflection layer (42) for improved light outfeed.
 21. Semiconductor chip according to claim 20, characterized in that the optical anti-reflection layer (42) is formed of silicon nitride.
 22. Semiconductor chip according to claim 20, characterized in that the optical anti-reflection layer (42) is formed of conductive indium-tin-oxide.
 23. Semiconductor chip according to one of the preceding claims, characterized in that the thin-film layer (2) comprises no cavity (8) in the region opposite one or more contact locations (7, 43).
 24. Semiconductor chip according to one of the preceding claims, characterized in that the mesas (4) taper in the direction toward the carrier substrate (1).
 25. Semiconductor chip according to claim 24, characterized in that the mesas (4) have a truncated pyramid or conoidal frustum shape and the oblique lateral surfaces comprises [sic] an angle of incidence φ relative to the lateral direction of extent of the thin-film layer (2) of between 5° and 60° , particularly between 10° and 40°.
 26. Semiconductor chip according to claim 25, characterized in that the angle of incidence φ lies between 15° and 30°.
 27. Method for the simultaneous manufacture of a plurality of semiconductor chips for optoelectronics having an active thin-film layer (2) wherein an active zone (3) that emits photons is formed, comprising the method steps: epitaxial growth of a layer sequence on a growth substrate wafer (20), said layer sequence containing a zone (3) that emits the photons; fashioning at least one cavity (8) in the layer sequence such that a plurality of mesas (4) arise in the layer sequence; applying at least one insulating layer (9) onto the surface of the layer sequence provided with the cavities (8); manufacturing at least respectively one through-contacting (12) on the mesas (4); applying the wafer union composed of growth substrate wafer (20) and layer sequence onto a carrier substrate wafer (21) such that the mesas (4) face toward the carrier substrate wafer (21), and connecting the wafer union to the carrier substrate wafer (21), particularly by means of soldering or gluing; at least partially removing the growth substrate wafer (20); applying an electrical contacting (7, 43, 49) onto that side of the layer sequence lying opposite the mesas (4); and separating the wafer union composed of carrier substrate wafer (21) and structured layer sequence along parting tracks (22) to form semiconductor chips (23).
 28. Method according to claim 27, whereby the layer sequence is parted along the parting tracks (22) before connecting the layer sequence to the carrier substrate wafer (21).
 29. Method according to claim 28, whereby the layer sequence is parted along the parting tracks (22) in a separate step before the connecting after the removal of the growth substrate wafer 20 and before the parting of the carrier substrate wafer (21). 